Previously, Samsung Electronics began volume production of 3-nm chips through a gate-all-around (GAA) process in June 2022, six months ahead of TSMC and a world first. Shocked by Samsung’s pre-emptive strike, TSMC executives publicly revealed their plan for a 2-nm process several times, triggering an ultra-fine fabrication race.
Intel, which announced its plan to re-enter the foundry business in 2021, has also joined the ultra-fine fabrication race. The U.S. semiconductor giant began to expand its presence in the foundry industry by announcing a technical overview, test data, and a roadmap on its wafer backside power supply solution, 'PowerVia,' in an online event on June 1 (local time). TSMC is also reportedly developing the technology to deliver power to the back of semiconductors with the goal of using it by 2026.
Intel has set a goal of advancing its foundry to make chips in the 1.8 nanometer range in the second half of 2024. In March, the company laid out a plan to develop a next-generation mobile system-on-chip (SoC) using the 1.8-nanometer process by forging a partnership with ARM. However, there is some pessimism among industry insiders that even if Intel succeeds in the process according to the roadmap, it will be a big challenge for the company to attain the desired yield to break even.
Samsung's Kyung Kye-hyun, president of the DS Division at Samsung Electronics, in a lecture at KAIST in Daejeon in early May, stated that the company plans to catch up with TSMC and gain technological advantage over the Taiwanese foundry giant beginning with their 2-nm process to which TSMC will start applying GAA technology.
In other TSMC news, the company announced today that their sixth advanced packaging and testing plant was officially opened, becoming the first all-in-one automated advanced packaging and testing facility in TSMC to realize 3DFabric integration of front-end to back-end process and testing services factory. At the same time, prepare for the mass production of TSMC-SoIC (system integrated chip) process technology. The sixth advanced packaging and testing factory will enable TSMC to have a more complete and flexible capacity planning for various TSMC 3DFabric advanced packaging and silicon stacking technologies such as SoIC, InFO, CoWoS and advanced testing, and bring higher production yield and performance synergy.
Dr. He Jun, Deputy General Manager of TSMC Operations/Advanced Packaging Technology and Service, Quality and Reliability, said, "Microchip stacking is a key technology to improve chip performance and cost-effectiveness, in response to strong market demand for three-dimensional integrated circuits (3DIC) , TSMC has completed the advance deployment of advanced packaging and silicon stacking technology production capacity, through the 3DFabric platform to provide technological leadership and production capacity that meets customer needs, and jointly realize cross-generational technological innovation, and become an important long-term trusted partner of customers.